A DMOS structure includes a drain region, a source region and a gate defined over a channel region. In the case of an N-channel device, the source-body region is formed with respect to a purposely defined opening in a polysilicon gate layer, and includes a P-body diffusion formed inside an N− pocket. A single or, more commonly, a shallow N− and a deeper N+ source diffusion are formed in succession in the P-body region. This is done by successive implants self-aligned to the definition edges of the poly (gate) opening and to the dielectric spacers successively formed there along according to well known VLSI and ULSI fabrication techniques. A source contact is formed on the N+ source diffusion. Of course, the types of conductivities are inverted in the case of a P-channel device.
Problems arise from the fact that in operation, and especially at relatively high currents, the potential of the N+ source diffusion tends to differ from the potential of the P-body diffusion containing it. These problems are addressed by locally short-circuiting the N+ source diffusion to the P-body by forming an electrical connection using a dedicated electrical connection P+ diffusion that extends in depth through the N+ source diffusion reaching down to the P-body region. This P+ diffusion of electrical connection is short-circuited to the N+ diffusion by a source contact formed thereon. Of course, the same considerations hold also for a P-channel device that is formed by inverting the types of conductivity (dopants) of the various regions.
With the advent of ULSI technologies, the size of the contacts has been reduced to allow for a greater density of integration, and as a result, the N+ and P+ diffusions could hardly be short-circuited using a single contact having a minimized or reduced cross section. Therefore, ULSI DMOS structures (N-channel or P-channel) generally have source regions provided with a plurality of minimum size contacts formed on the (N+ or P+) source diffusions, and larger size contacts on the local plug diffusions (P+ or N+) providing electrical connection to the body region. The local short-circuit between the P+ and N+ diffusions is established through the common source contact metallization.
Even a residual drawback of this approach causes current density non-uniformities in the source region because of charge carriers (electrons and holes) being collected through distinct contacts. This reduces the robustness of the device when operating at high currents because of a premature turning on of the intrinsic parasitic bipolar junctions transistor (NPN or PNP). This problem was successfully addressed by the invention disclosed in European patent application 158,583, which is incorporated herein by reference in its entirety and is assigned to the current assignee of the present invention.
According to the '583 patent application, an electrically conductive layer of silicide formed in a self-aligned manner (i.e., SAlicide) over the whole silicon surface in the source region area, effectively short-circuits the source (N+ or P+) diffusion and the plug diffusion (P+ or N+) of the electrical connection of the underlying body region. This is while the electric current eventually flows through one or more contacts formed on the silicide layer. According to a preferred embodiment of this technique, at least one source contact is projectively formed over the area of the plug diffusion (P+ or N+) of the electrical connection.
The layout of the contacts in the source region influences the on-resistance of integrated DMOS devices. For a typical layout of a DMOS device, the on-resistance per unit area of integration is proportional to the pitch distance between the source contacts and the drain contacts, and is inversely proportional to the width W of the drain and source regions. For a given width W of the drain and source regions, the on-resistance per unit area of integration may be lowered by reducing as much as possible the distance between such regions within the limits imposed by the manufacturing technology.
The layout of a DMOS structure is practically symmetrical for p-channel and n-channel devices. Basically, the layout is defined by four masks: the body mask which defines the opening through the polysilicon gate layer in correspondence to the source/body region of the structure; the contact (opening) and source (island) masks that are commonly designed at minimum lithographical dimensions; and the body contact mask, by which a sufficient effective distance from the polysilicon (gate electrode) edge of the plug of heavily doped silicon of a conductivity type opposite to that of the surrounding source region, reaching down in depth to contact the underlying body region, is defined to ensure adequate voltage withstanding characteristics.
Although the use of a SAlicide layer, with at least one source-body contact formed thereon, and if required, a plurality of spaced apart source contacts formed along the central axis in the width direction W of the opening through the polysilicon, has significantly helped in enhancing the resulting conductivity of an integrated DMOS structure. This has been accomplished in a very even distribution of the lines of current in the silicon toward the multiple source contacts, and reduces the width and pitch of the structure for comparable electrical performances. This approach has imposed the requisite of providing for the presence of a continuous heavily doped superficial region within the source region definition opening through the polysilicon to achieve an optimization of conduction characteristics. In fact, formation of a highly conductive layer of SAlicide thereon is favored by the presence of heavily doped silicon at the surface.
Such a requisite is generally fulfilled by the continuity of the relatively heavily doped source area implant (N+) surrounding the area of definition of the body contact plug diffusion. This area needs to be masked from the heavy source implant by a resist cap or island. This ensures continuity of a heavily doped silicon surface area along the W direction of the opening through the polysilicon layer.
Of course, the two sides of the body contact plug diffusion heavily implanted with a dopant (P+) of an opposite type of conductivity to that of the (N+) source dopant is to remain at a sufficient distance from the definition edge of the polysilicon (gate electrode) to preserve voltage withstanding characteristics of the integrated structure.
Therefore, on account of the alignment tolerances of three distinct masks that are normally used, the width of the opening in the polysilicon is to be made sufficiently large for ensuring a sufficient distance of separation between the side of the central mask window used for implanting the body contact plug diffusion dopant from the definition edge of the poly (gate). This inevitably limits the possibility of reducing the width in the pitch direction of the elongated openings through the polysilicon gate layer. The three distinct masks are as follows: the heavy source N+ implant mask for defining the area of the body contact plug diffusion; the contact opening mask; and the mask for implanting the dopant of the body contact plug diffusion and of the overlay that needs to be considered.
These technological constraints relative to the definition of features within the poly openings of the source regions limit the possibility of further reducing the pitch of integration, and therefore, of the overall level of compactness that can be achieved with a certain manufacturing technology. Also, the ability to reduce the on-resistance for unit area of integration of the structure is similarly limited.